FIG. 1 illustrates a general integrated circuit memory device 100, which includes a cell array 110, an X-decoder 120, a Y-decoder and data output unit 130, and a controller 140. The controller 140, which controls the cell array 110, the X decoder 120, and the Y-decoder and data output unit 130, supports write and read operations to and from the cell array 110. As known to those skilled in the art, the X decoder 120 performs row addressing to select a wordline included in the cell array 110 upon data writing or reading. Upon data writing or reading, the Y-decoder and data output unit 130 performs column addressing to select a bitline included in the cell array 110 and senses and amplifies read-out data DOUT.
As shown in FIG. 2, the cell array 110 includes a plurality of rows and columns of memory cells 111 and a plurality of bitline driving circuits 120 driving differential bitlines BL/BLB connected to the memory cells 111. An operation of the bitline driving circuit 120 will now be described with reference to a timing diagram of FIG. 3. The bitline driving circuit 120 includes a first sense amplification circuit 112, which includes N-channel metal oxide semiconductor field effect transistors (MOSFETs) MN0 and MN1, a second sense amplification circuit 113, which includes P-channel MOSFETs MP0 and MP1, an N-channel pull-down MOSFET 114, which provides a ground voltage VSS during an operation of the first sense amplification circuit 112, a P-channel pull-up MOSFET 115, which provides a voltage VCCA during an operation of the second sense amplification circuit 113, a first precharge circuit 116 for left cells, and a second precharge circuit 117 for right cells. A discrete memory cell 210 included in the memory cells 111 stores data received via an input/output (IO) line (not shown) into a capacitor upon writing or outputs data stored in the capacitor to the IO line during reading. A single memory cell can be selected by selecting a wordline WL0/WL1/ . . . /WLn-2/WLn-1 in response to row addressing and selecting a pair of bitlines BL and BLB in response to column addressing.
Upon reading/writing, the first and second precharge circuits 116 and 117 precharge the bitlines BL and BLB with a voltage precharge VBL in response to a pair of signals PEQL and PISOL and a pair of signals PEQR and PISOR, respectively. These signals represent equalization and isolation signals. Accordingly, as shown in FIG. 3, if a wordline WLn-1 is selected and activated to thereby cause a charge sharing between the memory cell 210 and the bitline BL/BLB, the first and second sense amplification circuits 112 and 113 receive the voltages VSS and VCCA from the MOFSETs 114 and 115, respectively, and sense and amplify voltages existing on the bitlines BL and BLB. At this time, when a column selection signal of a selected bitline is activated, the sense amplified signal is output to an IO line (not shown), and IO data transmitted to the IO line is sense amplified by an IO sense amplifier (not shown) once more and output to a data output (DQ) pad.
As semiconductor manufacturing and design techniques are advanced, a chip size of an integrated circuit memory device typically decreases, and a speed thereof typically increases. However, when transistors within the integrated circuit memory device are small, and a low voltage driving technique is adopted, leakage current or noise must be reduced and stable data sensing by a sense amplification circuit must be maintained.
In a general precharge and sense amplification scheme, a voltage VCCA/2 is used as the precharge voltage VBL. In the bitline pair BL/BLB receiving cell data from the memory cell 210, a level change of ΔVBL occurs as illustrated in Equation 1, before sense amplification. Sense amplification circuits 112 and 113 sense and amplify a voltage difference of ΔVBL between the bitlines BL and BLB and output a rail-to-rail voltage difference of VCCA. Equation 1 is:ΔVBL=(V cell−VBL)/(1+Cs/Cb)  (1)wherein Vcell denotes a voltage level stored in the memory cell 210, VBL denotes a precharge level (e.g., VCCA/2), Cs denotes a capacitance of a capacitor included in the memory cell 210, and Cb denotes a bitline (BL/BLB) parasitic capacitance.
However, in the present condition where an operating voltage of an integrated circuit memory device is reduced, there is a sensitivity limit in lowering threshold voltages of MOSFETs MP0, MP1, MN0, and MN1 in the sense amplification circuits 112 and 113. Below these limits, the sense amplification circuits may fail. It is also difficult to render a precharge voltage greater or smaller than the voltage VCCA/2 to increase gate-source voltages Vgs applied to the MOSFETs MP0, MP1, MN0, and MN1.
To make sense amplification circuits sense data with greater stability, the threshold voltages between N-channel MOSFETs MN0 and MN1 included in the first sense amplifier 111 must be consistent, and the threshold voltages between P-channel MOSFETs MP0 and MP1 included in the second sense amplifier 113 must also be consistent. A mismatch between threshold voltages of transistors may generate errors when data is sensed and amplified and re-stored upon periodic data refresh in an integrated circuit memory device. These errors may limit the performance of the integrated circuit memory device. Moreover, if a difference between the voltages on bitlines BL and BLB is smaller than an amount of mismatch (hereinafter, referred to as an offset) between threshold voltages of the N-channel MOSFETs MN0 and MN1 (after charge sharing by the memory cell 210) and the bitline BL or BLB, the sense amplification circuits may fail in normal data sensing and limit the reliability of data refresh operations.